Month: October 2018

So here’s where the next video stands.

First, as I noted in a previous blog post, I’ve settled on an 8080-like MPU with 6 8-bit registers and an internal 8-bit bus.

Now to make an internal 8-bit bus work, you nee a tri-state gate, a logic circuit which can be used to disconnect our logic gate from a common bus. The idea here is that you may have six things that can write their output to a single set of lines (the bus), but only one thing actually writes out to the bus at the same time.

Which I now have a successful design for.

I’ve also figured out the timing issues for the accumulator. Basically the accumulator register is always tied to the output of our ALU–but because you’re reading the results into the accumulator at the same time you’re writing the previous value as the output. So ideally we want an accumulator which can latch the results internally when a clock signal changes state–but doesn’t actually output the results until the clock state changes back.

An interesting side effect is that if you want to copy a value into the accumulator, it is easier to simply write the results through the ALU. Meaning we need a control state on the ALU that simply copies the input across. (On the other hand, it means instructions like the 8080 instruction SUB (IX+index) relatively easy, since once the address is loaded, the memory value at address IX+index passes through the ALU on its way to the accumulator.)

And that means the test ALU board I just sent off for fabrication (and which will probably have a one-month turnaround, because you can have it fast or have it cheap–but you can’t have both fast and cheap) is now out of date.

Don’t worry, I’ll explain all of this in an upcoming video.

I do plan to build separate boards for the regular registers (the B/C/D/E and F registers), and for the A register (which does not have a write-enable line, but does contain multiple latches to shift values on both the clock signal going high and going low).

The only other circuit I need is to develop 90 degree out of phase signal to properly time the loading of all of the registers and the ALU.

Once I have that tested, I can start putting together the next video.

So one of my goals of my series “Introduction To Digital Computers” is to show the design of a computer that can be built entirely out of NPN transistors. The idea is that by showing the design of a digital computer from the absolute ground up–from something you can hold in your hands rather than from some theoretical abstraction–it makes the design of a digital computer a concrete thing. And hopefully that makes the entire process of designing a digital computer more “real” rather than some abstraction in some textbook somewhere.

But I’m beginning to realize that if I’m going to design something from NPN transistors, I need to build the circuits to make sure they work. After all, there are a lot of designs purportedly showing designing gates using NPN transistors that simply will not work.

So I’ve started relying more on MacSpice and iCircuit to verify my designs.

That doesn’t go far enough.

So the other day I’ve spent some time building the final ALU.

The circuit diagrams (from Eagle) were translated into two 100mm by 100mm boards (since the 61 transistors and countless resistors don’t fit on one board), one board which contains the logic for the ‘S’ output line (the sum/difference, and AND/OR/XOR/NOT logic) and one board which contains the logic for the ‘C’ output line (the carry/borrow/shift logic). Both schematics as PDF files can be downloaded here: BitALU.zip

And the reason for the 100mm by 100mm boards is that Seeed Studio has an amazingly cheap deal on 100mm by 100mm boards. (But make the board a millimeter above the given size, the price jumps from $5/board to $50/board.) I think the way they can offer this deal is that they’re manufacturing their own boards for their own products–and they are selling leftover space on those sheets.

Hopefully the design is correct; after assembling one board and verifying it works correctly I plan to run off a set of 10, populate 8 of them, and assemble a fully working 8-bit ALU in order to verify the design.

I also plan to verify the design of the register circuits from the prior video, and actually assemble them.

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The target, in the end, is a computer which has 6 8-bit registers: an accumulator, a flags register, and four additional intermediate 8-bit registers B, C, D and E. This is similar to the 8080 MPU, though instead of an H/L register, the ultimate design will use a 16-bit IX register, a 16-bit PC register, a 16-bit stack pointer, and internal registers for processing microcode and latching intermediate results to and from main memory. (The design of the IX register will be limited only to those instructions necessary to maintain a call stack for C–which means we only really need instructions to push and pop IX from the stack, to copy SP to IX and back, and to access memory at a fixed 8-bit and 16-bit offset from IX. Of course this also implies that the B and C registers as well as the D and E registers can be combined to form a 16-bit address.)

But baby steps, baby steps.

So this means the next video may be delayed another few weeks so I can verify my designs.