On SR latches, D latches, and why most sites get edge-triggered circuits wrong.

So my latest two boards arrived, implementing four demonstration circuits using NPN transistors: a bistable circuit using two transistors (well, four–I need two more to drive the two LEDs), an SR gate using NOR gates, an SR gate using NAND gates, and a D latch: a latch which can be used to store a single bit of data, and most often used as a building block to build a register in a CPU.

I’ve just posted the pages.

And I’m building to something here.

Now I don’t mean to pick on the authors of this web site; I think they did a fantastic job with the artwork and with the explanations of how different types of digital electronic circuits work.

It’s just that the article is dead wrong when it describes J-K flip-flops. A mistake that is made on multiple web sites across the Internet. (Example 1) (Example 2) (Example 3)

Screenshot 2023 01 08 at 9 33 14 PM

Notice the article itself even admits there is a problem with their design:

The JK flip flop is an improved clocked SR flip flop. But it still suffers from the “race” problem. This problem occurs when the state of the output Q is changed before the clock input’s timing pulse has time to go “Off”. We have to keep short timing plus period (T) for avoiding this period.

“We have to keep short timing plus period…”

What? What?

This is utter nonsense. And it was encountering articles like this that motivated me to start up the Hacking Den, and to actually build these circuits, in transistors, and to properly prototype them to make sure they work before posting what is, in essence, nonsense.

It’s why I’m holding off writing articles on NMOS, PMOS and CMOS circuits; I only just got the P-MOSFET transistors, and need to spend a little time breadboarding to verify the circuit works (without letting the magic smoke that allow these things to work escape). And it’s why I’m holding off articles on PNP transistor circuits; for some reason or another the bag of PNP transistors I ordered have yet to arrive in the mail.

Runqsbwxjn561


Getting your circuit to work with edge-triggered logic, by the way, is not just a couple of extra NAND gates and a whole bunch of wishful thinking. You can see how getting a circuit to respond to an edge-triggered signal by looking at the logic diagram associated with the 74LS74 TTL D-flip flop work (on page 3), or the 4013 CMOS D-flip flop.

Just a quick glance at the logic for these circuits in their documentation, and it’s clear there is far more to an edge-triggered flip flop than just some additional NAND gates.


It’s also important to remember that a lot of these circuits did not just fall fully formed from the forehead of Zeus, to grace us as fundamental facts of the universe, like the speed of light, the rising of the sun, or how buttered toast always lands butter-side down.

These circuits were designed and engineered to function according to certain required functionality. JK latches did not just fall from the sky; somewhere someone needed a latch which functioned like a JK latch–and someone designed and built it.

And designed it they did: you really have to appreciate the complexity of a 4027 series CMOS J-K flip flip.

Screenshot 2023 01 08 at 9 41 01 PM

This is hardly the 4 NAND gates in the “clocked SR flip flop” example those various informative–but incorrect–web sites.


Bottom line is you have to prototype your circuits before teaching people the wrong stuff.

Otherwise, what are you but a pretty face spewing garbate?

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William Woody

I'm a software developer who has been writing code for over 30 years in everything from mobile to embedded to client/server. Now I tinker with stuff and occasionally help out someone with their startup.

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