D Latch

From the SR latch we can construct a D latch, or a data latch. This is a latch which stores one bit of information, and unlike the SR latch, does away with the “undefined” state from its inputs.

We do this by using two additional AND gates on our SR latch, and adding an ‘enable’ line to enable storign the data.


Screenshot 2023 01 08 at 8 44 58 PM

Notice the AND gates are both off so long as the ‘enable’ input button is off. But the moment the ‘enable’ button is turned on, the ‘data’ line is fed to ‘set’, and its inverse to ‘reset’, which then sets the state of our SR latch according to the state of the input data.

If we were to expand the AND gates into their component NAND and NOT gates, and expand our SR gates into their appropriate NOT and NAND gates:

Screenshot 2023 01 08 at 8 54 11 PM

Notice how we have two NOT gates in a row? Yeah, we can eliminate them, giving us our final design for our D latch:

Screenshot 2023 01 08 at 8 56 08 PM

This is why it’s useful to build an SR latch using NAND gates rather than with NOR gates; because the NOT gates that are required to create the correct logic table–with both inputs off causing the circuit to maintain its state–wind up being eliminated as we create more and more complex circuits.

Now, using the transistor circuits in our section on NAND gates, we can turn this into a transistor-based circuit, wire it up, and we get the following data storage circuit: